Scan/ATPG Applicant should be familiar with scan hardware compressions, failure mechanisms and debug processes AC scan (at speed) development, debug, test and characterization Array Applicant should be familiar with modern SRAM cell operation. SRAM debug, characterization, test or design knowledge Memory BIST engine knowledge Analog/Mixed Signal Applicant should be famili

Isolate generic system level failures into a more focused area of the platform or CPU Drive debug and resolution of Zen CPU validation issues across silicon, firmware/BIOS, and coordinating with memory partners as needed Devise validation strategy from pre silicon through customer adoption working across architecture, silicon design, firmware, validation, and debug teams

Work with AMD's architecture specialists to improve future products. The ideal candidate will be responsible for writing high performance GPU kernels for AMD's Composable Kernel (https //github.com/ROCmSoftwarePlatform/composable_kernel) Performance Portable Programming Model for Machine Learning Tensor Operators. They will be developing and optimizing algorithms for new

Work with a team of micro architects , designers, and firmware engineers for developing C++ compiler for innovative embedded RISC V CPUs Performance investigation under various graphics and ML workload Implement compiler optimization for chip design flows Implement mechanisms for hierarchical caching Collaborate with hardware architects to develop the approach and design

Engage with external and internal customers, development teams and various architects to lead system feature requirement analysis, feature definition, firmware responsibility partition and cross component interface design, provide design documents and guidance Lead Engineer responsible for designing, developing, debugging, verifying and/or validating firmware, software an

Minimum of 10 years' experience in leading design teams in system level design, from concept to component selection and schematic capture through layout, bring up, debug, validation to high volume production. Experience working in dynamic, ever changing fast paced environment Strong cross functional collaboration a must Strong background in high speed board designing for

Design, develop, and debug BIOS (System Software), UEFI Firmware, VBIOS or Memory Firmware for internal/external systems and platforms that use AMD APU/CPU, AMD chipset, and 3rd party chipsets. Participant in day to day BIOS development / debugging work using PC assembly and C languages; will need to interact with internal organizations, BIOS vendors, and customers. Must

Perform RTL design, including micro architecture definition of the digital portions of the IP and drive for optimum power, performance, and area. Work closely with functional verification team to meet coverage and quality standards. Setup CDC checks, analyze and resolve CDC issues in the design. Work closely with methodology and PD teams to implement RTL design into GDSII

Plan and execute programs focusing on quality and deadlines Drives completion of all required deliverables, with a focus on customer quality feedback and established deadlines Creates and maintains project management artifacts such as schedule, resource and resource forecast, risk and issues logs Provides unique views of project status updates and facilitates cross develo

Counsel engineering clients regarding the use of open source software in compliance with policies and procedures. Review, draft, and negotiate inbound and outbound software and technology license agreements. Review, draft, and negotiate agreements for product sales, services, and support in addition to other customer and business partner contracts. Coordinate deal negotia

Develop technical specifications and processes for the DPPM Data Center to identify manufacturing issues and logical failures. Create software for the At scale automated test DPPM Data Center, collaborating with platform, silicon, debug tools, IT teams, and other stakeholders. Drive continuous technical improvements in testing, failure identification, and the debugging pr

Define and execute test cases for GPU Virtualization Create and maintain automation test framework for KVM/HYPER V/VMWare hypervisor Analyze and narrow down issues found during test Conduct sanity test, integration test, solution test, Performance test, stress test Reproduce and analyze issues reported by customers PREFERRED EXPERIENCE Knowledge of Windows and Linux envir

Participate and play critical role in planning project deliverables Own and drive software design, development, verification and release the product to customers Performing individual goal planning and evaluation in accordance with AMD policies Develop and grow the engineering skills of the team Drive critical issues and interface with cross functional teams PREFERRED EXP

GPU Kernel Optimization Develop and optimize low level GPU kernels to accelerate inference and training of large machine learning models. Maximize the computational efficiency and reduce execution time while ensuring model accuracy. Multi GPU and Multi Node Optimization Design and implement strategies for distributed model training and inference across multiple GPUs and n

Provide advisement and coordination for RPPG leadership team to drive decision making processes and execution of the strategic business objectives. Develop collaterals (presentations, pre reads, communications) for the CVP on internal and external activities through original contribution and/or collaboration with executives and senior leaders across RPPG. Represent the CV